The present invention relates to the circuitry for the testing and fine-tuning integrated circuit. In particular, the present invention relates to circuit for the control of switches in an integrated circuit.
In integrated circuits, test circuits are implemented to test and to make fine adjustments. For instance, a nonvolatile memory in a new chip may have an initial endurance of five thousand endurance cycles, each cycle including an erasure step (releasing electron) and a programming step (trapping electrons). By controlling the amount of electrons entering the floating gates in nonvolatile memory cells in each cycle, it is possible to dramatically increase the endurance of the nonvolatile memory. The amount of electrons entering the floating gates can be regulated by varying the bitline and wordline voltages. Therefore, by fine-tuning the bitline and wordlines voltages, one can increase the endurance of the nonvolatile memory.
FIG. 1 shows a test circuit for controlling the voltage of a wordline 12 of a flash memory device. The test circuit is implemented with a set of resistors, R1, R2, . . . , Rn, having different resistances and a fuse block 10. Each resistor in the test circuit is connected to the drain of a NMOS transistor, F1, F2, . . . , Fn. The source of each NMOS transistor connects to a ground while the gate of each NMOS transistor connects to the fuse block 10. The NMOS transistor functions as a fuse-activated switch, that is, depending on the output signal from the fuse block 10, it either connects or disconnects its corresponding resistor to ground. The resistors, R1, R2, . . . , Rn, are carefully chosen to provide an incremental set of wordline voltages. To obtain a desirable wordline voltage 12, an iterative process is used whereby the NMOS transistors, F1, F2, . . . , Fn, are activated individually or in a group until the desired wordline voltage is detected at the output 12.
Presently, the fuse block circuit 10 is implemented using nonvolatile memory cells, which, in addition to having endurance issues, requires supporting circuitry such as charge pumps and timing circuits that take up valuable chip space. Therefore, it would be desirable to have a fuse block circuit 10 that does not have endurance issues and does not require an excessive amount of supporting circuitry.
The present invention controls a plurality of switches through the outputs of a plurality of flip-flops. The flip-flops may be connected in a serial manner wherein the states are shifted into each flip-flop through an input terminal of the first flip-flop in the chain. Alternative, the state of each flip-flop could be loaded individually. The state in each flip-flop is applied from its output terminal to the gate of a corresponding transistor acting as a switch. The input terminal of the first flip-flop may be connected to a two-input multiplexer, wherein the first input terminal of the multiplexer connects to a data input terminal for the purpose of shifting states into the flip-flop chain and the second input terminal of the multiplexer connects to the output of the last flip-flop, providing a return path for the states during a read-out.